Low Power Design with High Level Power Estimation and Power Aware Synthesis By Sumit Ahuja and Avinash Lakshminarayana and Sandeep K. Shukla
Designing low-power computing hardware has always been a priority since the early 1990s. The famous graph drawn by Intel’s Shekhar Borkar is now imprinted in the minds of designers. It was realized that as the clock speed is scaled from mega hertz to giga hertz, the heat density on the surface of silicon chip would compare with that of rocket nozzles to the surface of the sun. Computing in today’s era has become pervasive in the form of handheld devices, smart phones, tablet computers, and most importantly bio implantable devices. Borker’s graph aptiy captures the need for reducing heat dissipation subsequently battery life conservation. The battery life of devices that are implanted inside one’s body must be sufficient to not require surgical substitution every few years. The wireless sensor network technology deployed for reconnaissance purposes by the military or for disaster management scenarios also brought in the requirement of long battery life despite the energy expensive communication functionalities.
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